| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 198 | Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors Authors:D. MOUNICA, S. VAISHALI, G. BABU |
1032-1040 |
Download | |
| IJVDCS 199 | Fully Reused VLSI Architecture of Fm0/Manchester Encoding using Sols Technique for DSRC Applications Authors:RUBEENA TAHSEEN, B. RANJITH KUMAR, G. BABU |
1041-1044 |
Download | |
| IJVDCS 200 | Design and Implementation of SOLS Techniques Based FM0 And Manchester Encoding using Clock Gating Authors:MATTA ANNAPURNA, DR. S.V.R.K.RAO |
1045-1049 |
Download | |
| IJVDCS 201 | Design and Hardware Implementation of Watermarking using Lifting Based DWT Technique Authors:M. BRAHMARAJU, S. JAGADEESH, G. SRIDEVI |
1050-1054 |
Download | |
| IJVDCS 202 | Performance Analysis of 4-2 Compressor and 5-2 Compressor Using Multiplication Authors:DALAI GOWRI SANKAR RAO, K.JAYARAM KUMAR |
1055-1057 |
Download | |
| IJVDCS 203 | Design of RAM using Pulsed Latch Based Shift Register Authors:PENUMAKA MOUNIKA, P. SOUNDARYA MALA |
1058-1061 |
Download | |
| IJVDCS 204 | Design and Implementation of 16-Bit MAC Ternary Multiplier Authors:K. SEETA RAMA RAJU, P.SURYA KUMARI |
1062-1065 |
Download | |
| IJVDCS 205 | High Speed Low Power MTCMOS D-Latch Based 32-Bit Carry Select Adder using 10-T Full Adder Authors:SAMBARAJU SNEHA, P.KALYANI, DR. D.NAGESHWAR RAO |
1066-1069 |
Download | |
| IJVDCS 206 | A Modern Design of PRPG in Presto Generator for On Chip Testing Authors:B. VEERABABU, DEVIREDDY VENKATARAMI REDDY, T. SARITHA |
1070-1077 |
Download | |
| IJVDCS 207 | Low Power and Area Shift Register using Pulsed Latches Authors:M. SWAPNA, P. SURESH KUMAR, K. SUREKHA |
1078-1082 |
Download | |
